Frequency Response for MOSFET/BJT

 

The frequency response of a BJT or MOSFET can be found using nearly the exact same process, with the only variations being caused by a single resistor and simple naming conventions that differ between the two devices.
Before we start let's think a little bit about what we're doing:
Our goal is going to be to find the pole(s) of the circuit.
Okay? What is a pole and why do I care where it is?
A pole is a frequency at which the gain of the device rolls off. (remember that when it rolls off , it will be at the -3dB frequency with a slope of -20dB/decade)
We care because if the gain of a device rolls off at a certain frequency, then we won't be able to amplify a signal above that frequency very well because the gain will be decreasing by 20dB/decade.
The procedure is nearly identical whether we are using a BJT of a MOSFET, but we will work each of them side by side just in case there might be any confusion, and we'll follow these steps as we go through.  (we will also use some values that came from the output file when running a simulation of this circuit in Cadence (or PSPICE) )

1. Take a look at one of the circuits and see what you notice, how about the MOSFET.  This step is just to help us with our knowledge understanding of the circuit.
- At a glance it just looks just like another MOSFET right? Sure is, but let's take a look at a few things just for kicks. Notice that it is using a bypass capacitor at the source so we don't have to worry about (at when working with high frequency).  Since the capacitor bypasses to ground, you should notice that this is a common-source amplifier.  You could notice the Values for and and start to think about what the Gate voltage is and how that may affect the circuit.
2. We are talking about frequency response so that means we are probably going to want to draw the small signal equivalent circuit.
Remember that the capacitors and will act like short circuits at high frequencies so we will ignore them, but we will have to account for some of the capacitance internal to the device.
Both devices have internal capacitances that are very similar.  As you can see from the small signal models for a MOSFET (above) and BJT (below), the only significant difference is that the BJT has an additional resistance Rpi between the Base and Emitter.
Most of the analysis we will do is based on the small signal model. Note that small signal models are not typically used in PSPICE so this picture may look a bit odd, especially the controlled source but for our purpose it is good to have a visual reference. To start we will point out what everything is. Cgs is an internal capacitance betwe
en the gate and source. The
values for Cgs was similar to one the a PSPICE simulation may give.  CM1 and CM2 are Miller capacitances which we will find values for later.  ro is a Norton equivalent resistance that makes the model more ideal.  And just pretend that the G2 looks more like a voltage controlled current source and that their gains are gm*Vgs and gm*Vpi. For the BJT CM1 and CM2 are both Miller capacitances, Cpi is similar to Cgs and Rpi the additional component used for BJTs but not MOSFETs. The other part should look familiar from the other figures.
ON TO THE ANALYSIS!!!
We will find the device gain, overall gain, equivalent input and output capacitances, and the input and output poles. The process for both is essentially the same.
Device Gain: This is the gain from the control source to the output so we are looking for Vout/Vgs (or Vout/Vpi for a BJT). We will ignore CM2 for this process. Notice the resistances ro, RD, and RL are in parallel. Vout should be given by that equivalent resistance times the current though it which is gm*Vgs from the control source. So the equation for device gain is,
   (MOSFET)
  (BJT)
Overall Gain: This will be the gain from the source (Vs) to the output (Vout). We already know what Vout/Vgs is so if we find Vgs/Vs, we can multiply them to get Vout/Vs = (Vout/Vgs) * (Vgs/Vs).  Vgs/Vs is a simple voltage divider. Hopefully you can see this from the small signal model (remember that we are ignoring the capacitors for now but they will play a part later).  The equations we will get for Vgs/Vs and the overall gain are.
  (MOSFET)
Overall Gain:   (MOSFET)
  (BJT)
Overall Gain:   (BJT)
Now we will find the input and output poles.  For this we will need to look at the capacitances and use a formula to find the Miller capacitances, CM1 and CM2.  Any explanation for the miller capacitance will have to wait for another post or check out your Electronics Book, Wikipedia, Google, etc. but we will need to use a couple of special equations.  Overall we will need to find the input resistance and input capacitance for the input pole and the output resistance and output capacitance for the output pole.
Each pole will be at a frequency w=1/RC where the R and C are the equivalent R and C at that point, so to find the input pole, we will need to find the input resistance and the input capacitance.  These are found by looking into the input (the left side of the small signal model).  The voltage source will  act like a short so we see Rs in parallel with R1//R2 for the MOSFET (the BJT will have Rpi in parallel also).  The input capacitance will be Cgs in parallel with CM1 (the BJT will be the same).  The output resistance and capacitance are found the same way only looking in from the output (the right side of the small signal model).
      (MOSFET or BJT)
So the input pole will be: (MOSFET)
  =  950                                     =
  =                                               =
=                                                                          =
(BJT)
and the output pole will be: (MOSFET)
(BJT)
=                                  =
=                                                 =

=                                        =

ELABORADO POR:

NERWIN ANTONIO MORA REINOSO

C.I: 17.557.095

EES

SECCION 1

CASCODE

 

The cascode is a two-stage amplifier composed of a transconductance amplifier followed by a current buffer. Compared to a single amplifier stage, this combination may have one or more of the following advantages: higher input-output isolation, higher input impedance, higher output impedance, higher gain or higher bandwidth. In modern circuits, the cascode is often constructed from two transistors (BJTs or FETs), with one operating as a common emitter or common source and the other as a common base or common gate. The cascode improves input-output isolation (or reverse transmission) as there is no direct coupling from the output to input. This eliminates the Miller effect and thus contributes to a much higher bandwidth.

History

The cascode (sometimes verbified to cascoding) is a universal technique for improving analog circuit performance, applicable to both vacuum tubes and transistors. The word "cascode" is a contraction of the phrase "cascade to cathode". It was first used in an article by F.V. Hunt and R.W. Hickman in 1939, in a discussion for application in low-voltage stabilizers.[1] They proposed a cascode of two triodes (first one with common cathode, the second one with common grid) as a replacement of a pentode.

Operation

Figure 1: N-channel cascode amplifier with resistive load (neglecting biasing details)

Figure 1 shows an example of cascode amplifier with a common source amplifier as input stage driven by signal source Vin. This input stage drives a common gate amplifier as output stage, with output signal Vout.

The major advantage of this circuit arrangement stems from the placement of the upper Field Effect Transistor (FET) as the load of the input (lower) FET's output terminal (drain). Because at operating frequencies the upper FET's gate is effectively grounded, the upper FET's source voltage (and therefore the input transistor's drain) is held at nearly constant voltage during operation. In other words, the upper FET exhibits a low input resistance to the lower FET, making the voltage gain of the lower FET very small, which dramatically reduces the Miller feedback capacitance from the lower FET's drain to gate. This loss of voltage gain is recovered by the upper FET. Thus, the upper transistor permits the lower FET to operate with minimum negative (Miller) feedback, improving its bandwidth.

The upper FET gate is electrically grounded, so charge and discharge of stray capacitance Cdg between drain and gate is simply through RD and the output load (say Rout), and the frequency response is affected only for frequencies above the associated RC time constant: τ = Cdg RD//Rout, namely f = 1/(2πτ), a rather high frequency because Cdg is small. That is, the upper FET gate does not suffer from Miller amplification of Cdg.

If the upper FET stage were operated alone using its source as input node (i.e. common-gate (CG) configuration), it would have good voltage gain and wide bandwidth. However, its low input impedance would limit its usefulness to very low impedance voltage drivers. Adding the lower FET results in a high input impedance, allowing the cascode stage to be driven by a high impedance source.

If one were to replace the upper FET with a typical inductive/resistive load, and take the output from the input transistor's drain (i.e. a common-emitter (CE) configuration), the CE configuration would offer the same input impedance as the cascode, but the cascode configuration would offer a potentially greater gain and much greater bandwidth.

Stability

The cascode arrangement is also very stable. Its output is effectively isolated from the input both electrically and physically. The lower transistor has nearly constant voltage at both drain and source and thus there is essentially "nothing" to feed back into its gate. The upper transistor has nearly constant voltage at its gate and source. Thus, the only nodes with significant voltage on them are the input and output, and these are separated by the central connection of nearly constant voltage and by the physical distance of two transistors. Thus in practice there is little feedback from the output to the input. Metal shielding is both effective and easy to provide between the two transistors for even greater isolation when required. This would be difficult in one-transistor amplifier circuits, which at high frequencies would require neutralization.

Biasing

As shown, the cascode circuit using two "stacked" FET's imposes some restrictions on the two FET's—namely, the upper FET must be biased so its source voltage is high enough (the lower FET drain voltage may swing too low, causing it to leave saturation). Insurance of this condition for FET's requires careful selection for the pair, or special biasing of the upper FET gate, increasing cost.

The cascode circuit can also be built using bipolar transistors, or MOSFETs, or even one FET (or MOSFET) and one BJT. In the latter case, the BJT must be the upper transistor; otherwise, the (lower) BJT will always saturate (unless extraordinary steps are taken to bias it).

Advantages

The cascode arrangement offers high gain, high slew rate, high stability, and high input impedance. The parts count is very low for a two-transistor circuit.

Disadvantages

The cascode circuit requires two transistors and requires a relatively high supply voltage. For the two-FET cascode, both transistors must be biased with ample VDS in operation, imposing a lower limit on the supply voltage.

Dual-gate version

A dual-gate MOSFET often functions as a "one-transistor" cascode. Common in the front ends of sensitive VHF receivers, a dual-gate MOSFET is operated as a common-source amplifier with the primary gate (usually designated "gate 1" by MOSFET manufacturers) connected to the input and the 2nd gate grounded (bypassed). Internally, there is one channel covered by the two adjacent gates; therefore, the resulting circuit is electrically a cascode composed of two FETs, the common lower-drain-to-upper-source connection merely being that portion of the single channel that lies physically adjacent to the border between the two gates.

ELABORADO POR:

NERWIN ANTONIO MORA REINOSO

C.I: 17.557.095

EES

SECCION 1

INTRODUCTION TO BJT

What is a Transistor?

A Transistor is an electronic device
composed of layers of a semiconductor
material which regulates current or
voltage flow and acts as a switch or gate
for electronic circuit.


History of the Transistor

P-N Junction
Russell Ohl 1939

First Transistor
Bell Labs 1947

Shockley, Brattain,
and Bardeen

First Solid State
Transistor – 1951





Processor development followed Moore's Law

1965 30 Transistors

1971 15,000

2000 42 million

2x growth every 2 years

Applications

• Switching

• Amplification

• Oscillating Circuits

• Sensors

ELABORADO POR: 

NERWIN ANTONIO MORA REINOSO 

C.I: 17.557.095 

EES 

SECCION 1

Silicon bipolar junction transistors (BJTs)

 

Silicon bipolar junction transistors (BJTs) technology has been a dominant RF power device in solid-state pulsed amplifiers up to L-band frequencies for many years. They can currently achieve at least 1-kW of peak RF power in push-pull operation. Of the technologies that are potential alternatives to silicon BJTs in this application – VDMOS, GaAs, SiC, LDMOS, and most recently GaN, only LDMOS has thus far proven competitive. That is, LDMOS can deliver the required RF output power, high efficiency, gain, and linearity, along with ruggedness over wide-ranging operational conditions. As a result, LDMOS FETs are making significant headway in replacing BJTs in solid state amplifiers operating in Class C mode at frequencies up to 1400 MHz. A comparison of the two technologies (Table 1) shows the strengths of each. Two of the 50-V LDMOS devices, for 450 and 1200 to 1400 MHz, designed and manufactured by Freescale show the performance LDMOS can achieve for pulsed applications.



Freescale has for several years been working on increasing the frequency range of the 50V technology, and has produced a family of devices for operation at frequencies from UHF through L-band. The first example is the MRF6VP14300H, which delivers 330 W from 1200 to 1400 MHz with a 300 µs pulse width signal and 12% duty cycle at 150 mA quiescent current bias. It was the first reported LDMOS device to deliver this performance at this frequency. Power density is 1.89 W/mm, drain efficiency is more than 59%, and gain is 14 dB in Class C operation. Rise time is less than 60 ns and pulse droop only 0.4 dB. Thermal resistance is 0.13ºC/W and junction temperature remains below 100º C at a flange temperature of 65º C. Power gain and efficiency versus output power at 1.4 GHz is shown in Figure 1.

The MRF6VP14300H employs internal matching for both the input and output side of the transistor to transform the die level impedance, which makes it easy for the designer to match the transistor input and output impedances to 50 ohms across the 1.2 to 1.4 GHz band. The internal input match consists of a two-section, lowpass T-network, and the internal output match consists of a single shunt inductor in series with a capacitor, which can improve output bandwidth.

The device can handle 3-dB input power overdrive and can withstand a 5:1 VSWR mismatch with full phase variation under a 3-dB overdrive condition. With the built-in enhanced ESD protection circuit, the device can operate in Class C with 14 dB of gain. The gate threshold voltage is typically around 1.6 V. Figure 2 shows the test results of Vgs sweep from 1.11 V to 2.23 V, and the operation class shifts from C to B to AB. Input power ranges up to 15 W, which is 3 dB higher than the typical maximum input power of 7.5 W. Power gain in Class C is 3 dB lower than for Class AB although power gain and output power nearly converge when the input power is greater than 12 W.

Figure 3 shows the gain and output power at Vgs of 0.84 V to 1.11 V and 12% duty cycle. Quiescent current is 3 mA. The device is operated in Class C at different Vgs and gain is close at higher input powers. However, the device provides isolation when input power is lower than 500 mW at Vgs of 0.84 V, which is very important for the stability of the host system. The pulse waveform of a pulsed transmitter is its core "ingredient', so slow transistor rise time and power droop within the pulse will produce a commensurate droop at the transmitter output, with a serious negative effect on system performance. This is important as well because many transistors are combined to produce the final output. Rise time of the MRF6VP14300H is less than 60 ns and pulse droop less than 0.4 dB from 1.2 to 1.4 GHz.

1 kW Performance at 450 MHzThe MRF6VP41KH is another example of Freescale's 50-V capabilities, this time at 450 MHz. It can deliver 1 kW peak RF output with a 300-us pulse width (20% duty cycle) input signal. Efficiency is greater than 60% and gain is 17 dB at 450 MHz in Class C operation. It will handle a VSWR of 5:1 with 300 and 500 µs pulses at a 20% duty cycle. In fact, this device can be used in CW applications, where it can deliver 1kW at 352MHz.

The MRF6VP41KH is designed in a push-pull configuration. There is no internal-matching capacitor at the input and output (device output capacitance is less than 150 pF), so that an external matching network can be used to achieve high performance over a wide bandwidth. While LDMOS FETs have been very successful in wireless infrastructure applications in Class AB mode (where high linearity is critical), their performance in class C is also quite remarkable.An on-chip circuit that provides considerable protection from electrostatic discharge (ESD) makes the device less susceptible to stray voltage during design and production. It provides the additional benefit of accepting a wide range of gate voltages from -6 to +10 VDC, which improves its performance when operates in Class C mode. The device has been built to accommodate both flanged (Figure 4) and earless packages to suite specific applications.

A comparison of the measured performance of the LDMOS device in Class AB, Class B, and Class C operation is shown in Figure 5. Output power and power gain versus input power are shown for a 300-µs pulse width and 20% duty cycle at 450 MHz under different Vgs conditions, effectively shifting operation from Class C to Class B. The device shows good linearity before the P1dB point and power gain remains near constant over a 3-dB range of input power (10 to 20 W). Power gain converges after input power increases to more than 22 W. Figure 6 illustrates efficiency at different Vgs bias conditions and is greater than 60% with input power greater than 18 W at 450 MHz. The droop performance at 450 MHz of the MRF6VP41KH is less than 0.3 dB at room temperature when delivering 1 kW of RF power. Rise time is less than 500 ns and fall time is less than 100 ns.

SummaryThe silicon BJTs has earned its solid position in lower-frequency pulsed power amplifiers (and other applications as well) through its ability to deliver high power with very good performance in nearly all the parameters that matter most. However, LDMOS devices are encroaching on the territory that is currently the BJT's near-exclusive domain, and will increase their penetration of this market because of their superior long-term "roadmap" to greater performance and higher frequencies as well as competitive specifications in nearly every area. The two devices described in this article are currently in production at Freescale, and more information is available at our website.

ELABORADO POR: 

NERWIN ANTONIO MORA REINOSO 

C.I: 17.557.095 

EES 

SECCION 1

Transistor Physics

• Composed of N and P-type Semiconductors

• N-type Semiconductor has an excess of
electrons
– Doped with impurity with more valence electrons
than silicon

• P-type Semiconductor has a deficit of
electrons (Holes)
– Doped with impurity with less valence electrons
than silicon

P-N Junction (Basic diode):

- Bringing P and N Semiconductors in contact
- Creation of a Depletion Zone

P-Type N-Type

• P-N Junction
• Reverse Biased => No Current
• Applying –ve Voltage to Anode increases
Barrier Voltage & Inhibits Current Flow

• P-N Junction
• Forward Biased => Current Flows
• Applying +ve Voltage > Barrier Voltage to
Anode allows current flow


• Basic Transistor


Water pipe analogy






Properties of the BJT

Common emitter configuration

2 basic laws:

Ie=Ib+Ic
Ic=β.Ib (β=10 to 100)


Operating Point

• Amplifier mode
• Switching mode

ELABORADO POR: 

NERWIN ANTONIO MORA REINOSO 

C.I: 17.557.095 

EES 

SECCION 1